A serial peripheral interface flash (SPI Flash) is capable of synchronously performing serial data transmission with a processor through an SPI interface. Through the SPI interface, the processor is capable of performing read and write operations on the SPI Flash. The SPI interface needs only four signal cables, namely, a chip select (CS) signal cable, an SPI clock (SCLK) signal cable, a master output slave input (MOSI) signal cable, and a master input slave output (MISO) signal cable, so that pin resources of the processor are saved.
Generally, when the SPI Flash is performing an erase operation or a programming operation, even if the processor sends a read instruction to the SPI Flash, the Flash refuses to respond. Under this mechanism, after the processor started by using the SPI Flash is reset completely, the processor begins to read software code data from the SPI Flash. If the Flash is performing an erase operation before the processor is reset and the SPI Flash does not finish the erase operation when the processor is reset completely and begins to read software code data, the Flash refuses to respond to a read data instruction sent from the processor, that is, no data is output in a data output signal cable of the SPI Flash, while the processor considers that the data read operation is already completed. Therefore, the processor may read incorrect software code data from the SPI Flash, and incorrect software codes are run, which results in that programs of the processor are run incorrectly or a system cannot be started, thereby greatly reducing reliability of the system.